(1) Field of the Invention
The present invention relates to the formation of integrated circuit devices on semiconductor substrates, and more particularly a method of fabricating a field effect transistor having a self-aligned anti-punch-through implantation.
(2) Description of the Prior Art
In recent years advances in semiconductor processing technology as resulted in Ultra Large Scale Integration (ULSI) on the semiconductor substrate. For example, advances in high resolution photolithographic techniques and advances in plasma etching have resulted in feature sizes that are less than a half micrometer in size. One application of this down scaling on the semiconductor chip where the reduction in size dramatically improves performance of the circuit and increases device density on the chip is the formation of the gate electrode of the field effect transistor (FET). The reduced width of the gate electrode has resulted in channel lengths under the gate electrode becoming submicrometer in size.
Although the down scaling improves circuit density and performance, a number of short channel effects can occur that adversely affect device performance. For example, the major transistor phenomena that are affected by down scaling and degrade the transistor behavior include channel-length modulation, velocity saturation, mobility degradation, source/drain resistance, punchthrough, drain induced barrier lowering and dependence of threshold voltage (V.sub.t) on device geometry.
When the channel length is reduced and is comparable in length to the source/drain junction depth, a considerable amount of the space charge, under the gate electrode, is linked to the source/drain junction depletion region. This results in less charge in the space-charge region being coupled or linked to the gate and the threshold voltage V.sub.t of the FET decreases. To minimize the threshold voltage V.sub.t variation with reduced channel length, it is common practice in the semiconductor industry to fabricate FET structures with Lightly Doped Drains (LDD). These LDD regions are formed adjacent to the gate electrode by doping using ion implantation. Sidewall insulating spacer on the gate electrode then mask the LDD region from further doping, while the heavier doped source/drain contacts are formed.
However, other short channel effects, such as punchthrough, still remain a serious problem. In this effect when the sum of the source and drain depletion widths formed in the substrate become greater than the channel length, the source and drain are electrically shorted together and the basic transistor action, as a switch is lost. Another short channel length effect that is closely related to the widening of the depletion width at the drain for a FET device that is turned-off, is Drain-Induced Barrier Lowering (DIBL) that occurs at the source end of the channel. This barrier lowering effect can result in increased leakage currents when the FET is in the off or non-conducting state. This can cause failure in dynamic circuits, and especially in DRAMs where charge retention is critical.
One method that is commonly practice in the semiconductor industry to prevent punchthrough is to form an anti-punchthrough buried implant channel in the substrate by ion implantation in the device area. This method is best understood by referring to the prior art as depicted in FIGS. 1 through 3. Starting with FIG. 1, a patterned silicon nitride/pad oxide stack is formed on the substrate 10 by photolithographic techniques and etching, leaving portions of the silicon nitride layer 14 and pad oxide layer 12 on the device areas and removing the stack layer elsewhere on the substrate where the Field OXide (FOX) isolation is to be formed. A deep anti-punchthrough buried channel 16 is formed in the substrate, for example, by implanting boron ions, such as isotope (B.sup.11) and depicted in FIG. 1 by the down ward pointing arrows.
A conventional LOCOS (LOCal Oxidation of Silicon) method is then used to form the field oxide (FOX) structure. The method consisting of thermally oxidizing the substrate using the silicon nitride layer 14 as a barrier to oxidation over the device area. After forming the field oxide (FOX) structure 18, as shown in FIG. 2, the silicon nitride layer 16 and pad oxide 12 are removed and a good quality gate oxide layer 20 is thermally grown on the device area. The gate electrode 22 of the FET is then formed by depositing and patterning a polysilicon layer 22 using a patterned photoresist layer 24 and plasma etching.
As shown in FIG. 3, the photoresist is stripped and Lightly Doped Drain (LDD) source/drain regions 26 are formed by ion implantation of arsenic or phosphorus ions. The field effect transistor (FET) is then completed by forming sidewall spacers 28 over the LDD regions adjacent to the gate electrode and then forming the N.sup.+ doped source/drain contact 30.
Although the anti-punchthrough buried implant channel reduces punchthrough from drain to source, the increased junction capacitance resulting from the anti-punchthrough channel extending under the source/drain contact 30, degrades the circuit performance. Therefore, there is still a strong need in the semiconductor industry for improved methods of forming anti-punchthrough buried implant channels with reduced capacitance.